cicyt UNIZAR

Hardware Architecture

Authors and titles for recent submissions

[ total of 7 entries: 1-7 ]
[ showing up to 25 entries per page: fewer | more ]

Wed, 21 Feb 2018

[1]  arXiv:1802.02138 (cross-list from cs.CV) [pdf, other]
Title: Musical Chair: Efficient Real-Time Recognition Using Collaborative IoT Devices
Subjects: Computer Vision and Pattern Recognition (cs.CV); Hardware Architecture (cs.AR)

Tue, 20 Feb 2018

[2]  arXiv:1802.06195 [pdf]
Title: High Speed SRT Divider for Intelligent Embedded System
Comments: IEEE Int. Conf. Soft Comp. 17 (5 Pages)
Subjects: Hardware Architecture (cs.AR)

Mon, 19 Feb 2018

[3]  arXiv:1802.05982 (cross-list from eess.SP) [pdf, other]
Title: Residual-Based Detections and Unified Architecture for Massive MIMO Uplink
Authors: Chuan Zhang (1 and 2 and 3), Yufeng Yang (1 and 2 and 3), Shunqing Zhang (4), Zaichen Zhang (2 and 3), Xiaohu You (2) ((1) Lab of Efficient Architectures for Digital-communication and Signal-processing (LEADS), (2) National Mobile Communications Research Laboratory, (3) Quantum Information Center, Southeast University, China, (4) Shanghai Institute for Advanced Communications and Data Science, Shanghai University, Shanghai, China)
Comments: submitted to Journal of Signal Processing Systems
Subjects: Signal Processing (eess.SP); Hardware Architecture (cs.AR); Computational Engineering, Finance, and Science (cs.CE); Numerical Analysis (cs.NA)

Thu, 15 Feb 2018

[4]  arXiv:1802.05100 [pdf, other]
Title: SAPA: Self-Aware Polymorphic Architecture
Comments: Boston Area Architecture 2018 Workshop (BARC18)
Subjects: Hardware Architecture (cs.AR); Software Engineering (cs.SE)

Wed, 14 Feb 2018

[5]  arXiv:1802.04576 [pdf, ps, other]
Title: Polar-Coded Forward Error Correction for MLC NAND Flash Memory Polar FEC for NAND Flash Memory
Authors: Haochuan Song (1 and 2 and 3), Frankie Fu (4), Cloud Zeng (4), Jin Sha (5), Zaichen Zhang (2 and 3), Xiaohu You (3), Chuan Zhang (1 and 2 and 3) ((1) Lab of Efficient Architectures for Digital-communication and Signal-processing (LEADS), (2) Quantum Information Center of Southeast University, (3) National Mobile Communications Research Laboratory, Southeast University, China, (4) Lite-On Technology Corporation, Guangzhou, China, (5) School of Electronic Science and Engineering, Nanjing University, China)
Comments: submitted to SCIENCE CHINA: Information Sciences
Subjects: Hardware Architecture (cs.AR)
[6]  arXiv:1802.04657 (cross-list from cs.LG) [pdf, other]
Title: Analyzing and Mitigating the Impact of Permanent Faults on a Systolic Array Based Neural Network Accelerator
Comments: To appear at IEEE VLSI Test Symposium 2018
Subjects: Learning (cs.LG); Hardware Architecture (cs.AR); Computer Vision and Pattern Recognition (cs.CV); Neural and Evolutionary Computing (cs.NE)
[7]  arXiv:1802.04259 (cross-list from cs.CR) [pdf, other]
Title: Sphinx: A Secure Architecture Based on Binary Code Diversification and Execution Obfuscation
Comments: Boston Area Architecture 2018 Workshop (BARC18)
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[ total of 7 entries: 1-7 ]
[ showing up to 25 entries per page: fewer | more ]

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