cicyt UNIZAR

Hardware Architecture

Authors and titles for recent submissions

[ total of 15 entries: 1-15 ]
[ showing up to 25 entries per page: fewer | more ]

Tue, 20 Mar 2018

[1]  arXiv:1803.06958 [pdf, other]
Title: Techniques for Shared Resource Management in Systems with Throughput Processors
Subjects: Hardware Architecture (cs.AR)
[2]  arXiv:1803.06955 [pdf, other]
Title: AISC: Approximate Instruction Set Computer
Subjects: Hardware Architecture (cs.AR)
[3]  arXiv:1803.06617 [pdf, other]
Title: Towards an Area-Efficient Implementation of a High ILP EDGE Soft Processor
Authors: Jan Gray, Aaron Smith
Subjects: Hardware Architecture (cs.AR)
[4]  arXiv:1803.06913 (cross-list from cs.LG) [pdf, ps, other]
Title: Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration
Comments: 13 pages with Appendix
Subjects: Learning (cs.LG); Hardware Architecture (cs.AR)

Mon, 19 Mar 2018

[5]  arXiv:1803.06185 [pdf, other]
Title: The ARM Scalable Vector Extension
Comments: 8 pages, 8 figures, IEEE Micro paper
Journal-ref: IEEE Micro ( Volume: 37, Issue: 2, Mar.-Apr. 2017 )
Subjects: Hardware Architecture (cs.AR); Performance (cs.PF)
[6]  arXiv:1803.06068 [pdf, other]
Title: Memory Slices: A Modular Building Block for Scalable, Intelligent Memory Systems
Subjects: Hardware Architecture (cs.AR); Performance (cs.PF)
[7]  arXiv:1803.06305 (cross-list from cs.DC) [pdf, other]
Title: C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs
Comments: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR); Computer Vision and Pattern Recognition (cs.CV); Numerical Analysis (cs.NA)

Fri, 16 Mar 2018

[8]  arXiv:1803.05900 (cross-list from cs.CV) [pdf, other]
Title: Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions
Comments: Accepted for publication at the ACM Computing Surveys (CSUR) journal, 2018
Subjects: Computer Vision and Pattern Recognition (cs.CV); Hardware Architecture (cs.AR); Learning (cs.LG)
[9]  arXiv:1803.05849 (cross-list from cs.CV) [pdf, other]
Title: XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks
Subjects: Computer Vision and Pattern Recognition (cs.CV); Hardware Architecture (cs.AR)

Thu, 15 Mar 2018

[10]  arXiv:1803.05320 (cross-list from cs.DC) [pdf, other]
Title: Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR)
[11]  arXiv:1803.05132 (cross-list from cs.ET) [pdf, other]
Title: Neuron inspired data encoding memristive multi-level memory cell
Journal-ref: Analog Integrated Circuits and Signal Processing, 2018
Subjects: Emerging Technologies (cs.ET); Hardware Architecture (cs.AR); Neural and Evolutionary Computing (cs.NE)
[12]  arXiv:1803.05131 (cross-list from cs.ET) [pdf, other]
Title: Feature extraction without learning in an analog Spatial Pooler memristive-CMOS circuit design of Hierarchical Temporal Memory
Journal-ref: Analog Integrated Circuits and Signal Processing, 2018
Subjects: Emerging Technologies (cs.ET); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Neural and Evolutionary Computing (cs.NE)

Wed, 14 Mar 2018

[13]  arXiv:1803.04862 (cross-list from eess.SP) [pdf, other]
Title: Correlation Manipulating Circuits for Stochastic Computing
Comments: 6 pages, 5 figures, 4 tables, Design, Automation and Test in Europe Conference and Exhibition (2018)
Subjects: Signal Processing (eess.SP); Hardware Architecture (cs.AR)
[14]  arXiv:1803.04786 (cross-list from cs.DC) [pdf, ps, other]
Title: A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors
Comments: Published in IEEE Transactions on Parallel and Distributed Systems. arXiv admin note: text overlap with arXiv:1802.05123
Journal-ref: IEEE Transactions on Parallel and Distributed Systems ( Volume: 29, Issue: 1, Jan. 1 2018 ) Page(s): 2 - 15
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR)
[15]  arXiv:1803.04783 (cross-list from cs.DC) [pdf, other]
Title: A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets
Comments: 16 pages, submitted to IEEE Transactions on Computers journal
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR)
[ total of 15 entries: 1-15 ]
[ showing up to 25 entries per page: fewer | more ]

Disable MathJax (What is MathJax?)