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Computer Science > Hardware Architecture

Title: The ARM Scalable Vector Extension

Abstract: This article describes the ARM Scalable Vector Extension (SVE). Several goals guided the design of the architecture. First was the need to extend the vector processing capability associated with the ARM AArch64 execution state to better address the computational requirements in domains such as high-performance computing, data analytics, computer vision, and machine learning. Second was the desire to introduce an extension that can scale across multiple implementations, both now and into the future, allowing CPU designers to choose the vector length most suitable for their power, performance, and area targets. Finally, the architecture should avoid imposing a software development cost as the vector length changes and where possible reduce it by improving the reach of compiler auto-vectorization technologies. SVE achieves these goals. It allows implementations to choose a vector register length between 128 and 2,048 bits. It supports a vector-length agnostic programming model that lets code run and scale automatically across all vector lengths without recompilation. Finally, it introduces several innovative features that begin to overcome some of the traditional barriers to autovectorization.
Comments: 8 pages, 8 figures, IEEE Micro paper
Subjects: Hardware Architecture (cs.AR); Performance (cs.PF)
Journal reference: IEEE Micro ( Volume: 37, Issue: 2, Mar.-Apr. 2017 )
DOI: 10.1109/MM.2017.35
Cite as: arXiv:1803.06185 [cs.AR]
  (or arXiv:1803.06185v1 [cs.AR] for this version)

Submission history

From: Stuart Biles [view email]
[v1] Fri, 16 Mar 2018 12:16:36 GMT (853kb,D)